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Chapter 2 Test Structure Basics Contents 2.1 CMOS Circuit Elements and Scaling . . . . . . . . . 2.1.1 MOSFETs and Diodes . . . . . . . . . . . . 2.1.2 Precision Resistors and Capacitors . . . . . . . 2.1.3 Interconnects . . . . . . . . . . . . . . . . 2.1.4 Physical Layout and Ground Rules . . . . . . 2.1.5 CMOS Logic Gates . . . . . . . . . . . . . 2.1.6 CMOS Scaling Rules . . . . . . . . . . . . . 2.2 Electrical Measurements and Test Equipment . . . . . 2.3 Silicon Interface to Test Equipme
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  Chapter 2 Test Structure Basics Contents 2.1 CMOS Circuit Elements and Scaling . . . . . . . . . . . . . . . . . . . . . . 132.1.1 MOSFETs and Diodes . . . . . . . . . . . . . . . . . . . . . . . . . 132.1.2 Precision Resistors and Capacitors . . . . . . . . . . . . . . . . . . . . 152.1.3 Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.1.4 Physical Layout and Ground Rules . . . . . . . . . . . . . . . . . . . 182.1.5 CMOS Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . 182.1.6 CMOS Scaling Rules . . . . . . . . . . . . . . . . . . . . . . . . . . 212.2 Electrical Measurements and Test Equipment . . . . . . . . . . . . . . . . . . 232.3 Silicon Interface to Test Equipment . . . . . . . . . . . . . . . . . . . . . . 242.3.1 Probe Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262.3.2 Advanced Probing Techniques . . . . . . . . . . . . . . . . . . . . . 292.3.3 Macro Area and Test Time Efficiency . . . . . . . . . . . . . . . . . . 292.4 Nuts and Bolts of Test Structure Macro Designs . . . . . . . . . . . . . . . . . 302.4.1 I/O Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322.4.2 Signal Propagation Delay of CMOS Logic Gates . . . . . . . . . . . . . 342.4.3 Wire R, C, and L . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372.4.4 Buffer (Driver) Sizing and Noise Reduction . . . . . . . . . . . . . . . 422.4.5 I/O Drivers and ESD Circuits . . . . . . . . . . . . . . . . . . . . . . 442.4.6 Power Supply Distribution . . . . . . . . . . . . . . . . . . . . . . . 462.4.7 Differential Measurement Schemes . . . . . . . . . . . . . . . . . . . 522.4.8 Commonly Used Circuit Blocks . . . . . . . . . . . . . . . . . . . . . 532.5 Macro Templates and Design Methodology . . . . . . . . . . . . . . . . . . . 572.5.1 DUT Designs and P cells . . . . . . . . . . . . . . . . . . . . . . . . 572.5.2 Discrete Element Macros . . . . . . . . . . . . . . . . . . . . . . . . 582.5.3 One-Dimensional Array Macros . . . . . . . . . . . . . . . . . . . . . 592.5.4 Two-Dimensional Array Macros . . . . . . . . . . . . . . . . . . . . . 602.5.5 High-Speed Macros . . . . . . . . . . . . . . . . . . . . . . . . . . 622.5.6 Scaling of Macro Designs . . . . . . . . . . . . . . . . . . . . . . . 63References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6411M. Bhushan, M.B. Ketchen, Microelectronic Test Structures for CMOS Technology ,DOI 10.1007/978-1-4419-9377-9_2, C  Springer Science+Business Media, LLC 2011  12 2 Test Structure Basics Electrical measurements are made either by directly contacting the test structure ona silicon wafer to the test equipment as shown in Fig. 2.1 or after dicing and pack-aging the test structure. The design of test structures is therefore closely coupled tothe method of interfacing to the test equipment and the capabilities and limitationsof the test equipment itself. Design and test efficiency is improved by standardiz-ing the footprints of each class of test structures and maintaining a high degree of commonality among them. Many of the test structures for MOSFET and CMOScircuit characterization may be implemented at the first level of metal. During tech-nology development and manufacturing, feedback from such test structures early inthe process cycle can help reduce the fabrication cost of CMOS products.In this chapter, the essential elements of electrical test structures in CMOS tech-nology are introduced. Special emphasis is placed on integrating the design effortwith silicon area usage constraints and test requirements. The concepts presentedhere for achieving efficiency in design, data acquisition, and analysis are followedthroughout the book.The following terminology is used loosely throughout the book. A device undertest (DUT) is the circuit element or the circuit block to be characterized. A DUTmay be a MOSFET, a resistor, a ring oscillator, a CMOS circuit block, or a num-ber of these circuit elements and blocks connected together to form a single unitsuch as an array of MOSFETs. A test structure comprises a DUT and peripheralcircuitry required for carrying out the measurements. A macro contains one or moretest structures, assembled together as a single unit to be placed on silicon. The teststructures within a macro may share peripheral circuits and I/O pads to improvesilicon area utilization and test efficiency.In Section 2.1, a brief description of CMOS circuit elements and basic logicgates is given followed by CMOS technology scaling rules. The types of testequipment used in the manufacturing line and in the laboratory are introduced inSection 2.2. Silicon-to-test equipment interfaces, which include metal probes andpackages, are discussed in Section 2.3. Nuts and bolts of macro designs covered inSection 2.4 include I/O pads, signal propagation in logic gates and interconnects, test equipmenttest structures onsilicon wafertester-to-siliconinterface Fig. 2.1 Interfacing testequipment to test structureson silicon  2.1 CMOS Circuit Elements and Scaling 13 on-chip buffers, I/O drivers, power distribution, and commonly used logic circuitblocks. The concept of macro templates, design methodology, and tips on migratingmacros from one technology node to another are described in Section 2.5.We have assumed that the reader is familiar with at least some aspects of CMOStechnology,circuitdesign,andtest.Foranin-depthtreatmentofthesetopics,werec-ommend standard textbooks on CMOS fundamentals [1–3], semiconductor devicesincluding MOSFETs [4, 5], microelectronic fabrication [6, 7], and semiconductorcharacterization [8]. 2.1 CMOS Circuit Elements and Scaling The two key constituents of digital CMOS circuits are the complementaryMOSFETs, n-FET (NMOS), and p-FET (PMOS), configured to consume powerprimarily during switching. A p/n diode is another active element used in I/O protec-tion, voltage reference, and isolation circuits. Precision resistors are used in CMOSanalog circuit applications such as amplifiers, analog-to-digital (A/D) converters,and phase-locked loops for internal clock generation. Metal oxide semiconductor(MOS) capacitors serve as decoupling capacitors for power supply stabilization.Parasitic resistances and capacitances associated with MOSFETs and metal inter-connects have a measurable impact on circuit behavior. These parasitic elements arecharacterized and modeled along with the other active and passive circuit elements.  2.1.1 MOSFETs and Diodes Physical schematic cross sections of an n-FET and a p-FET in a conventional bulk silicon technology are shown in Fig. 2.2a. The source, S, and drain, D, electrodesor terminals of the n-FET are formed with heavily doped n-type diffusion, or n+,regions in a p-type body or p-well. Similarly, S and D electrodes of the p-FETare formed with p+ diffusion in an n-type body or n-well. The voltage on the gateelectrode, G, which is separated by a thin oxide layer (not shown) from the chan-nel region between S and D terminals controls the source-to-drain current of theMOSFET. Contact to the body, B, of the MOSFET is made through a p+ diffu-sion layer for a p-type body and through an n+ diffusion layer for an n-type body.Both n-well and p-well may be electrically isolated from the substrate in a twin-well(twin-tub) process.Physical layout schematics of an n-FET and a p-FET are shown in Fig. 2.2b ina standardized format used throughout the book. Only the key design layers areshown to preserve clarity in the drawings. The drawings are not to scale. Outlineof the n-well is shown for the p-FET, which distinguishes it from the layout of the n-FET. Layer DF denotes the n+ and p+ diffusion layers, PS is the gate layer,and H0 squares represent vias connecting DF and PS to the first metal layer M1through a dielectric isolation layer. Each MOSFET has two PS electrodes connected  14 2 Test Structure Basics oxideSp-dopingn+n-wellp-type silicon substrateSGDM1G(a)(c)D(b)DGSBp+BBBGSGD   Gn+p+n+p+n-dopingp-dopingBGBSGG(d)n-FETp-FETH0H0M1PSDFn-wellDSDSDSD PSPS PSPS oxide oxide Fig. 2.2 An n-FET and a p-FET: a schematic cross sections, b physical layouts, c circuit symbolswith S, D, G, and B terminals, and d circuit symbols with S, D, and G terminals in parallel (two-finger design), the outer DF regions form the S terminal and theregion between the fingers is the D terminal. The drain-to-source current I  ds is mod-ulated by the voltages on the G and D terminals with respect to the S terminal, V  gs and V  ds , respectively. The I  ds increases as the width W  of the MOSFET is increasedor its channel length L p is reduced.Circuit symbols for the n-FET and the p-FET with terminals S, D, G, and B areshown in Fig. 2.2c. The B terminal is connected to an independent power supplyto control the body-to-source voltage V  bs if a twin-well process is used. In mostcircuits, terminal B is connected to S ( V  bs = 0 ) and three terminal representations
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